1. Field of the Invention
This invention relates to a static type semiconductor memory device and a method of manufacturing the same, and, more particularly, a static type semiconductor memory device having a number of memory cells each including a pair of field effect transistors each having a gate electrode cross-coupled with a drain region connected to a power source terminal by way of a load resistor, and the method of manufacturing the same. Above all, it relates to an improvement in the structure of the memory cell.
2. Description of the Prior Art
As the static type semiconductor memory device, a so-called static random access memory, referred to hereinafter as SRAM, is well known. FIG. 1A is a block diagram showing the overall structure of such conventional SRAM. FIG. 1B is an equivalent circuit diagram showing a memory cell of the SRAM shown in FIG. 1A. FIG. 1C is a block diagram showing the flow of data in the SRAM shown in FIG. 1A. Meanwhile, FIG. 1A shows an example of an 8 kiloword .times.8 bit SRAM.
Referring to FIG. 1A, the SRAM shown therein includes a memory cell array 101 including a plurality of memory cells 50 acting as storage locations, an X decoder 102 and a Y decoder 103 connected to associated address buffers for selecting the addresses of the memory cells, and an input/output interface section including sense amplifiers connected to the output buffer. Each of the memory cells 50 as the storage portions is connected at an intersection of a bit line pair connected to the Y decoder 103 and a word line connected to the X decoder 102 in a matrix configuration for constituting the memory cell array 101. Responsive to the column address signals and the row address signals applied from outside, one of the memory cells 50 at the intersection of each bit line pair and each word line selected by the X decoder 102 and the Y decoder 103 is selected.
More specifically, responsive to an input address signal, a normal signal (X) and a reverse signal (X) are produced in the address buffers. Responsive to the X and X signals, the X decoder 102 selects one of the 256 columns, charges the word line of that column to High and discharges all other word lines to Low. The memory cell 50 of the selected column is thereby activated to output the data therein to each bit line and bit line. Only one of bit line--bit line pair of 32 bit line--bit line pairs of each channel is connected to a I/O line--I/O line pair by way of a multiplexer. The selection is performed by the Y decoder 103. In this manner, only the desired 8-bit memory cells are connected to the I/O line.
When writing data, the input data are entered into the thus selected memory cell 50. On the other hand, when reading out data, the data stored in the selected memory cell 50 are sensed and amplified by the sense amplifier so as to be outputted to outside as output data.
The data read-out and writing operation will be explained in more detail by referring to FIG. 1C. As shown in FIG. 1A, the sense amplifier and the write driver are connected to the I/O line, and data are transmitted in the direction of the solid line arrow mark during read out and in the direction of the dotted line arrow mark during writing. There are a write enable signal or We signal and an output enable signal or I/0 signal acting, as it were, as valves for controlling the data flow, and adapted to control the write driver output to high impedance and the output buffer output to high impedance, respectively.
Referring to FIG. 1B, a flip-flop type memory cell is formed in one memory cell 50 by metal oxide semiconductor field effect transistors or MOSFETs (Q3, Q4) 33, 34 as two driver transistors each having its gate electrode cross-coupled to its draining region, and high resistance loads (R1, R2) 35, 36 connected to each drain region. Each of the two MOSFETs 33, 34 has its drain region connected to two MOSFETs (Q1, Q2) 31, 32 as two access transistors. Each of these MOSFETs 31, 32 has its gate electrode connected to the word line 43. When the word line 43 is in the selected state, the data stored in the MOSFETs 33, 34 is transferred via MOSFETs 31, 32 to a bit line 39 and a bit line 40. One of the memory cell modes 41 is connected to the drain region of the MOSFETs 43 and the gate electrode of the MOSFETs 34 via wire sections DW formed by an impurity-diffusion layer. The other memory cell node 42 is connected to the gate electrode of the MOSFETs 33 and the drain region of the MOSFETs 34 via wire sections PW formed by a polycrystal silicon layer. Each of the MOSFETs 33, 34 has its source region connected to a ground potential 38. On the other hand, each of the MOSFETs 33 and 34 has its drain region connected to a power source potential (Vcc) 37 via each of the high resistance loads 35, 36.
The MOSFETs 33, 34 are formed as a bistable flip-flop circuit by having the drain regions and the gate electrodes cross-coupled to each other so as to enable bit data to be stored. More specifically, a 1-bit data may be stored when one of the memory cell nodes 41 is at the "High" level potential and the other memory cell node 42 is at the "LOW" level potential, or vice versa. That is, when the word line 43 is at the "HIGH" level, the MOSFETs 31, 32 are in the turned-on state, so that the memory cell nodes 41, 42 are conductively connected to the bit lines 39, 40. At this time, the voltage associated with the states of the MOSFETs 33, 34 are generated on the bit lines 39, 40 by way of the MOSFETs 31, 32. In this manner, the data stored in the memory cell 50 is read out. When writing data in the memory cell 50, a voltage associated with the desired writing state is applied to each of the bit lines 39, 40, while the MOSFETs 31, 32 are in the turned-on state. Meanwhile, the flip-flop circuit constituted by the MOSFETs 33, 34 is supplied with the current from the source potential 37 by way of the high resistance loads 35, 36, for maintaining the storage state of the data latched in the flip-flop circuit.
FIG. 2 shows in plan view the pattern layout of the above described high resistance load type SRAM memory cell. FIG. 3 shows, in a simplified plan view, the pattern layout of the SRAM memory cell shown in FIG. 2.
Referring to FIGS. 2 and 3, an isolation region 1 is formed by an oxide layer of a larger film thickness on a semiconductor substrate. First polysilicon layers 2a, 2b 2c are formed on this isolation region 1. The first polysilicon layer 2a forms a word line and is used simultaneously as the gate electrodes of the MOSFETs 31 and 32 in regions other than the isolation region 1. The first polysilicon layers 2b, 2c form gate electrodes of the MOSFETs 33, 34, respectively. An N type impurity-diffusion region is formed in the regions of the P-type semiconductor substrate other than the isolation region 1 and the first polysilicon layers 2a, 2b, 2c.
Second polysilicon layers 4a, 4b, 4c are formed on the first polysilicon layers 2a, 2b, 2c with insulating layers interposed. The second polysilicon layer 4a forms a wiring from the MOSFETs 35, 36 to the source potential (Vcc) 37. The second polysilicon layer 4b is used as the cross-coupling wiring in the memory cell. This second polysilicon layer 4b interconnects the drain region of the MOSFET 34, the gate electrode 2b of the MOSFET 33 and the source region of the MOSFET 32 by way of a first buried contact hole 3b. The second polysilicon layer 4c interconnects the gate electrode 2c of the MOSFET 34 and the source region of the MOSFET 31 by way of a first buried contact hole 3c.
A third polysilicon layer 6, surrounded by a dotted chain line, is formed on the second polysilicon layers 4a, 4b, 4c with an insulating layer interposed. This third polysilicon layer 6 forms high resistance loads 35, 36. The third polysilicon layer 6 is connected to a wiring layer 4a in a power source potential (Vcc) 37 by way of a second buried contact hole 5a. This third polysilicon layer 6 is also connected to each of the memory cell nodes 41, 42 by way of second buried contact holes 5b, 5c.
The drain regions of the MOSFETs 31, 32 are connected by way of contact holes 7a, 7b to bit lines 39, 40 formed by aluminum or the like material.
FIG. 4 is a partial cross-sectional view taken along line IV--IV in FIG. 3 those portions of the MOSFETs 31, 32, 33, 34 that are formed after the formation of the gate electrode are not shown for simplifying the illustration. Referring to FIG. 4, n+diffusion regions 8a, 8b, 8c, 8d are formed on the main surface of the P-type silicon semiconductor substrate 9. Impurity-diffusion regions 8a, 8b represent the source and drain regions of the MOSFET 33. The impurity-diffusion regions 8c, 8d represent the drain and source regions of the MOSFET 34. The gate electrodes 2b, 2c are formed on the main surface of the silicon semiconductor substrate 9 with a gate oxide film 0 interposed.
In the above described conventional high resistance load type SRAM memory cell, it has been tried to miniaturize or reduce the size of its component of the device in keeping with the tendency toward higher integration of the memory device. Thus it has been tried to reduce the size not only in the horizontal direction along the main surface of the semiconductor substrate but in the perpendicular or laminating direction orthogonal to the main surface of the semiconductor substrate. This has given rise to the following various problems.
(a) Increased sheet resistance in the n+impurity-diffusion region
In keeping with miniaturization, the channel length of the MOSFETs tends to be reduced. Also, in keeping with miniaturization in the horizontal and the laminating directions, it has become necessary to reduce the thickness of the gate oxide film 10 or the n+diffusion regions 8a to 8d and to form the shallow n+-p junction. As the n+diffusion regions becomes shallow in this manner, the sheet resistance of the diffusion region is increased. As shown in FIGS. 1B, 2 and 3, this n+diffusion region is used as the wiring connection in the memory cell or as the wiring layer of the memory cell to the ground potential. For this reason, an increased parasitic resistance in this diffusion region affects the operation of the memory cell.
Referring to FIG. 2, the drain region of the MOSFET 33 is extended in the right upper direction so as to be connected with the gate electrode 2c of the MOSFET 34 and the source region of the MOSFET 31. On the other hand, the drain region of the MOSFET 34 is connected to the gate electrode 2b of the MOSFET 33 and to the source region of the MOSFET 32 by way of the second polysilicon layer 4b. In this manner, the cross-coupling wiring in the memory cell is made on one hand through the diffusion layer and on the other hand through the polysilicon layer. This produces asymmetricities in the memory cell which should be formed symmetrically in the left and right direction. Moreover, a high-resistance load is connected in series with the drain regions of the MOSFET 33 through the diffusion region, the current driving capability of the MOSFET 33 is substantially lower than that of the MOSFET 34. As a result, there is the risk that the bistable state of the flip-flop circuit can no longer be maintained.
Also, when reading out the data stored in the memory cell, the potentials corresponding to the states of the MOSFETs 33, 34 appear on the bit lines 39, 40 through the MOSFETs 31, 32. At this time, the charges corresponding to the respective potentials are discharged through the MOSFETs 31, 33 and MOSFETs 32, 34. However, the time involved in the discharging of the charges is prolonged due to the above described connection of the high resistance load through the diffusion region, thus resulting in the increase access time in the SRAM. In this case, one of the cross-coupling wiring is made through the diffusion region, so that the asymmetricities are produced in the memory cell due to increase in the parasitic resistance thereof.
(b) Increased sub-threshold current
It is known in general that, in MOSFETs when the channel length is shortened, the sub-threshold current is increased due to short channel effects. By the sub-threshold current is meant the drain to source current when the gate voltage is below the threshold voltage and the surface of the channel region is in the weakly inverted state. This sub-threshold current is treated as the channel leakage current.
Referring to FIG. 1B, when the potential of the word line 43 is at the "Low" level, the MOSFETs 31, 32 are in the turned-off state. At this time, considering data storage to the disregard of these MOSFETs 31, 32, the MOSFET 33 is turned-off state if, for example, the memory cell node 41 is at the "High" level potential and the memory cell node 42 is at the "Low" level potential. The memory cell node 41 is charged by the high resistance load 35 so that it is maintained at the "High" level potential. This enables the data to be stored.
In this case, for decreasing the power consumption of the chip in its entirety with integration of the memory device, it is necessary to increase the resistance value of the high resistance loads 35, 36. For example, in a 1-megabit SRAM, the resistance value per each high resistance load amounts to several T ohms. On the other hand, due to miniaturization in keeping with the higher integration of the memory device, the channel length of each MOSFET is decreased. As a result, the leakage current in the turned-off state of the MOSFETs 33, 34, which could be disregarded in comparison with the charging current flowing through the high resistance loads 35, 36, can no longer be disregarded with the increase in the sub-threshold current as described hereinabove. As a result, the above data storage becomes unfeasible.
(c) Junction leakage
As discussed in (b) above, the resistance values of the high resistance loads 35, 36 are suitably modified for maintaining the power consumption of the chip with this entirety at a reasonable level in keeping with the high integration of memory device. For example, when the integration degree of the memory device is quadruplicated, the resistance value of the high resistance load is increased proportionately thereto, that is, it is at least also quadruplicated. However, it is extremely difficult to reduce the leakage current of each MOSFET inversely proportionately, that is, to reduce the leakage current to one fourth. The reason therefor resides in the so-called junction leakage in addition to the above described sub-threshold leakage.
That is, as indicated by the drain regions 8b, 8c in FIG. 4, the drain region in each MOSFET forms necessarily an n+-p junction between it and the silicon semiconductor substrate 9. The reverse leakage at this p-n junction cannot be avoided physically. The junction leakage in this case is proportional to its junction area and the junction edge length, that is, the peripheral length of the junction when seen in plan view. A junction area may be reduced with miniaturization of the component device. However, the edge length cannot be reduced so markedly as the junction area. For this reason, it ie becoming extremely difficult to reduce the junction leakage.
(d) Increased soft error ratio
With miniaturization of the memory cell area, the area of the junction or the gate electrode for forming the capacitance at the memory cell nodes 41, 42 is increased proportionally. As a result, the node capacity is decreased in reverse proportion to the increase in the integration degree of the memory device. This decrease in the node capacity means the decrease in the charges stored in the memory cell nodes. As a result, the problem is presented that the SRAM becomes vulnerable to soft errors produced by noise charges of, for example, external .alpha.-rays.
(e) Isolation
With miniaturization of the component parts of the SRAM device, it becomes necessary to miniaturize the isolation with in the isolation region 1 simultaneously. This results in the lowered breakdown voltage and increased leakage current.